FIG. 1 depicts a schematic diagram of printed circuit board 100 on which are mounted two integrated circuits, integrated circuit 101 and integrated circuit 102, which are contained in dual in-line packages.
In accordance with the prior art illustration, some of the pins or pads on integrated circuit 101 are electrically tied, in well-known fashion, to some of the pads on integrated circuit 102. In particular:                pad 24 on IC 101 is connected to pad 8 on IC 102, and        pad 23 on IC 101 is connected to pad 9 on IC 102, and        pad 22 on IC 101 is connected to pad 9 on IC 102, and        pad 21 on IC 101 is connected to pad 10 on IC 102, and        pad 20 on IC 101 is connected to pad 1 on IC 102, and        pad 19 on IC 101 is connected to pad 2 on IC 102, and        pad 18 on IC 101 is connected to pad 7 on IC 102, and        pad 17 on IC 101 is connected to pad 6 on IC 102, and        pad 16 on IC 101 is connected to pad 5 on IC 102, and        pad 15 on IC 101 is connected to pad 4 on IC 102, and        pad 14 on IC 101 is connected to pad 3 on IC 102, and        pad 13 on IC 101 is connected to pad 12 on IC 102.        
FIG. 1 depicts one possible layout of the printed leads on printed circuit board 100 for accomplishing the requisite interconnections between integrated circuit 101 and integrated circuit 102 on a two-layer printed circuit board. This topology of interconnections consumes a great deal of space on printed circuit board 100 and is disadvantageous in that it causes the impedance of some lines to be different than the impedance of some others. In contrast, if all of the printed leads between two integrated circuits were parallel, less space would be consumed on the printed circuit board and the impedance of adjacent leads would be similar.
In particular, the flipping of a bus (e.g., pads 14 through 18 on integrated circuit 101 to pads 3 through 7, respectively, on integrated circuit 102, etc.) on a printed circuit board makes the layout of the printed circuit board difficult. Therefore, the need exists for an improved technique for routing printed leads on printed circuit boards between integrated circuits.